1. Field of the Invention
In integrated MOS circuits, those transistors with a minimal gate length are used as drivers, and transistors with a minimal width are used as active load elements. For load elements, the transistor width has a direct effect on the gate capacitance, which forms a capacitive load for the preceding stage, and the resistance value for an active load element. In prior art methods for producing integrated MOS circuits, the minimal transistor width is determined by the minimal active bulk width in the production of the field insulation by means of a LOCOS (Local Oxidation of Silicon) process. In a certain lithography generation, this is normally about one and a half to two times more than the minimal gate length.
A smaller transistor width is desired, however, since this has a positive effect on the transistor area, gate area and hence gate oxide yield and also on the input capacitance of the active load elements.
The cells of non-volatile memories such as FLOTOX EEPROMs or flash memories are also formed by MOS transistors, i.e., by elements having a source region, a channel region, and a drain region. The information is stored in such memory cells in a floating gate above the channel region, which is insulated from the latter by a gate oxide. This charge is changed by programming or erasure as a result of Fowler-Nordheim tunneling of electrons between the floating gate and the semiconductor substrate through a very thin dielectric, which is formed by a very thin window, the tunneling window, in the gate oxide. The requisite voltage, corresponding to a field strength of more than 10 MV/cm, is coupled in capacitively through a control gate.
The voltage across the control gate which is required for initiating the tunneling process depends on two factors: first, the efficiency with which the voltage applied to the control gate is coupled in, in other words on the coupling factor which is essentially determined by the ratio between the area of the control gate and the area of the tunneling window, and, second, on the thickness of the tunnel oxide.
A minimum programming voltage requires a small tunneling window with a thin tunnel oxide while calling for maximum overlap of the control gate over the floating gate.
Tunneling takes place in flash memory cells in a region of overlap between the floating gate and the drain region. Thinned oxide portions arise at the field oxide edges during the production of the gate oxide by thermal oxidation of the gate regions in the field oxide produced by means of a LOCOS process. The thinned oxide portions lead to non-homogeneous current injection and to reduced oxide reliability. These process-induced thinned portions must be prevented by a correspondingly thicker nominal tunnel oxide. In addition, the oxide thickness in the case of ultra-thin oxides is downwardly limited due to the occurrence of "anomalous gate leakage currents" after Fowler-Nordheim injection.
Accordingly, it is primarily necessary to reduce the size of the tunneling window in order to reduce the programming voltage, and in order to achieve a high coupling factor.
This may be done in two ways. On the one hand by reducing the region of overlap and on the other hand by reducing the channel width. The field insulation is usually effective by means of a LOCOS process, with the result that the channel width has a lower limit imposed on it by the structural resolution of the photolithographic process.
Tunneling in EEPROM memory cells takes place via a tunneling window in the gate oxide overlying the channel region. In this case, too, the dimensions of the window are limited by the structural resolution of the photolithography.
The Japanese disclosure JP 5-190809 A2 discloses the use of a spacer technology to etch mutually insulated trenches into an oxide-polysilicon-oxide-polysilicon layer structure applied to a semiconductor substrate, with the result that the width of the trenches becomes very small and the remaining structures constitute stacked gates with a high packing density. However, the dimension of the gate electrodes is in this case not influenced by the spacer technology.
The paper 28 IBM Technical Disclosure Bulletin, No. 6, November 1985, discloses the production of a GaAs FET having a gate electrode with a very short length. The length is determined by a spacer technology. However, the gate electrode is in direct contact with the channel region, thereby producing a Schottky contact. Moreover, a special layer structure is used to produce the Schottky gate electrode and it cannot easily be transferred to silicon MOS technology.